1. Field of the Invention
The present invention relates generally to a piezoelectric transformer circuit drive circuit and a piezoelectric transformer driving method. More particularly, the invention relates to a piezoelectric transformer circuit drive circuit and a piezoelectric transformer driving method taking a power source for a back-light of a display device employing a liquid crystal, as a load, or so forth.
2. Description of the Related Art
In general, a piezoelectric transformer is an element, in which primary side and secondary side electrodes are attached on a piezoelectric material to cause resonance of a transformer by applying a voltage of resonance frequency of the piezoelectric transformer on the primary side and to lead out a voltage generated by mechanical resonation on the secondary side. The piezoelectric transformer is characterized in capability of down-sizing and reduction of thickness in comparison with an electromagnetic transformer. Therefore, the piezoelectric transformer is an element attracting attention as a back-light power source for the display device employing a liquid crystal, or so forth.
The conventional drive circuit for a piezoelectric element of this type has been disclosed in Japanese Unexamined Patent Publication No. Heisei 9-107684. The disclosed drive circuit turns OFF a transistor in time division manner for interrupting an input voltage of the piezoelectric transformer for variably controlling a root-mean-square effective value of an alternating current or an alternating voltage to be supplied to the load which is connected to the piezoelectric transformer. The conventional drive circuit disclosed in the above-identified publication will be discussed with reference to FIG. 11.
As shown in FIG. 11, the conventional drive circuit includes a transformer circuit 4 having a piezoelectric transformer 1, in which a primary electrode 100 and a secondary electrode 200 are provided, a drive voltage control circuit 5 controlling a drive voltage for transforming, a frequency control circuit 3 for controlling a drive frequency, a dimmer circuit 6 for dimming when a load to be driven is a cold cathode tube.
In FIG. 11, the transformer circuit 4 drives the piezoelectric transformer 1 by resonating inductance and input capacitance of coils L1 and L2 of the piezoelectric transformer 1 and whereby generating a sine wave. Transistors Q1 and Q2 are alternately turned into ON state by clocks Vg1 and Vg2 of opposite phases output from a frequency divider circuit 8 to charge a current from a direct current power source VDD to the coils L1 and L2 as electromagnetic energy so that a voltage higher than the power source voltage can be generated as a voltage energy by discharging the charged energy upon turning OFF of the transistors Q1 and Q2. A half-wave sine wave of mutually different phase equivalently act as sine weave to vibrate the piezoelectric transformer 1 to output an elevated alternating current voltage V0 determined depending upon a shape of the piezoelectric transformer 1 from the secondary electrode 200.
The alternating current voltage V0 is applied to the load 2. Then, an alternating current IO is input to the frequency control circuit 3. The frequency control circuit 3 is a circuit performing a process for outputting a frequency data driving the piezoelectric transformer 1 to the frequency divider circuit 8 to continue sweeping of drive frequency until the alternating current IO fed back from the load reaches a predetermined value and for stopping the frequency, at which the predetermined value is obtained.
The frequency control circuit 3 is constructed with a current-voltage converting circuit 10, a rectifier circuit 11, a comparator 12, an integrator circuit 13, a comparator 14 and a voltage controlled oscillator (VCO) 15. The alternating current IO is converted into a voltage signal by the current-voltage converting circuit 10, rectified by the rectifier circuit 11 and then input to the comparator 12 as a detection signal. The comparator 12 compares the voltage of the detection signal with a reference voltage Vref. If the voltage of the detection signal is lower than the reference voltage Vref, a high level signal is output to the integration circuit 13. The integrator circuit 13 is designed to lower an output voltage at a given rate during a period where the high level signal is input. The output voltage Vin of the integrator circuit 13 is input to the VCO 15. From the VCO 15, a triangular wave fVCO and a rectangular wave fCLK are output. The output waveforms of the VCO 15 are illustrated in FIG. 12A(A). When a voltage Vin from the integrator circuit 13 is a minimum voltage value, 12A(A) illustrates the output voltage waveform as the triangular wave fVCO and 12A(B) illustrates the output voltage waveform as the rectangular wave fCLK. FIG. 12A(C) is a voltage waveform chart, in which the rectangular wave fCLK is processed by frequency division by the frequency divider circuit 8 of the transformer circuit 4 to be Vg1. While not illustrated, a signal Vg2 having opposite phase to the signal Vg1 is also generated by the frequency divider circuit 8. The frequency divider circuit 8 of the type, in which phases of the signal is reversed at the rising timing of fCLK, is premised. On the other hand, both of the triangular wave fVCO and the rectangular wave fCLK are set the frequencies thereof at a value double of the frequency for driving the piezoelectric transformer 1. FIGS. 12B(D), 12B(E) and 12B(F) respectively show fVCO. fCLK and Vg1 in the case where the voltage Vin from the integrator circuit 13 is maximum, which fVCO, fCLK and Vg1 are set for outputting higher frequency than those at the minimum voltage of Vin.
The reason why the output of the integrator circuit 13 is risen at a given rate to lower the output frequency of the VCO 15 in a period where the output of the comparator 12 is held high level, is to sweep the drive frequency from the high frequency side. The reason why sweeping the drive frequency from the high frequency side is to use the frequency region higher than the resonance frequency fr of the piezoelectric transformer 1. Thus, the step-up ratio of the piezoelectric transformer 1 is increased to increase of magnitude of the alternating current Io in time. At this condition, if the voltage input to the comparator 12 exceeds the reference voltage Vref, the output of the comparator 12 becomes low level to cause termination of the integrating operation of the integrator circuit 13. Thereafter, the output of the integrator circuit 13 is maintained at the immediately preceding voltage value. Accordingly, the frequency data output by the VCO 15 also becomes constant to drive the piezoelectric transformer at as constant drive frequency. Thus, the output of the piezoelectric transformer 1 is maintained constant.
When a direct current input voltage VDD less than a rated voltage is input to a piezoelectric transformer inverter or when a relatively long period is required to turn ON the cold cathode tube used in the load 2, the predetermined alternating current Io cannot be supplied to the frequency control circuit 3 while the direct current is supplied to lower the output frequency of the VCO 15 to be lower than or equal to the resonance frequency. Therefore, when the direct current input voltage is elevated to be higher than or equal to the rated voltage or when the cold cathode tube of the load 2 is turned ON, the step-up ratio of the piezoelectric transformer becomes insufficient to continue a condition where the predetermined output cannot be supplied to the load 2. Accordingly, when the drive frequency is lowered down to the minimum frequency of the VCO 15, it becomes necessary to return the drive frequency to the maximum frequency of the VCO 15. In this operation, when the output voltage of the integrator circuit 13 becomes lower than or equal to the reference voltage Vmin set at a value corresponding to the minimum frequency of the VCO 15, the output of the comparator 14 becomes high level to output a reset signal to the integrator circuit 13. In response to this reset signal, the output of the integrator circuit 13 becomes the maximum voltage to resume lowering of the frequency. Relationship between the transforming ratio of the piezoelectric transformer and the frequency sweeping direction are illustrated in FIG. 13. In FIG. 13, f1 is the maximum frequency and f2 is the minimum frequency. The foregoing operation is repeated until the predetermined alternating current Io is obtained as shown by arrow Y.
The drive voltage control circuit 5 is constructed with a comparator 16, a rectifier 17, a diode 18 and a transistor Q3 to control the peak current value to be supplied to the coils L1 and L2 of the transformer circuit 4 constant relative to fluctuation of the direct current input voltage and whereby to control the drive voltage of the piezoelectric transformer 1 at a predetermined value.
The rectifier circuit 17 is a circuit for rectifying the primary voltage waveform of the piezoelectric transformer 1 and then to convert into the voltage Vc. The rectified voltage Vc after conversion is input to the comparator 16. The triangular wave fVCO generated by the VCO 15 and having the frequency double of the piezoelectric transformer drive frequency is input to the comparator 16 of the drive voltage control circuit 5 to be compared with the rectified voltage Vc to apply a high level signal to a gate of the transistor Q3 during a period where the rectified voltage Vc is higher than the triangular wave fVCO.
Among timing charts shown in FIGS. 14(A) to 14(H), FIG. 14(A) shows the triangular wave fVCO and the rectified voltage Vc, FIG. 14(B) shows a gate voltage Vg3 of the transistor Q3, FIGS. 14(C) and 14(D) show gate voltages Vg1 and Vg2 of the transistors Q1 and Q2, FIGS. 14(E) and 14(F) are drain voltages Vd1 and Vd2 of the transistors Q1 and Q2, and FIGS. 14(G) and 14(H) show coil currents iL1 and iL2.
When the direct current input voltage VDD is elevated from this condition, the rectified voltage Vc is instantly increased to expand the period where Vg3 is held OFF to shorten a period for charging iL1 and iL2. By this, Vd1, Vd2, iL1 and iL2 are reduced to be controlled by the original values of the Vd1, Vd2, iL1 and iL2. Namely, even when the input voltage VDD is varied, the rectified voltage Vc relative to the triangular wave fVCO is varied significantly to cause variation of the duty ratio of the transistor Q3 to control the peak current to be charged to the coil constant and whereby to control the drive voltage of the piezoelectric transformer 1 at a predetermined value.
On the other hand, the dimmer circuit 6 is a circuit required in the case where dimmer control is necessary, such as back light using the cold cathode tube in the load. The dimmer circuit 6 is constructed with a triangular wave oscillation circuit 19 for oscillation at a frequency sufficiently lower than the drive frequency of the piezoelectric transformer 1 and a comparator 20. By externally inputting a dimmer control voltage Vbri, it is compared with an output waveform Vtri of the triangular wave oscillation circuit 19 in the comparator 20 to output a pulse signal Voff of variable duty ratio. This is shown in timing charts in FIGS. 15(A) and 15(B). The pulse signal Voff is fed to the frequency control circuit 3 and the drive voltage control circuit 5 to turn OFF the transistor Q3 in a period at high level thereof to interrupt the drive voltage for the piezoelectric transformer 1, and in conjunction therewith to hold the output voltage of the integrator circuit 13 so as not to vary the frequency of the VCO 15.
However, the foregoing prior arts encounter the following problems.
The first problem is significant limitation of a dimming range due to delay of output relative to the piezoelectric transformer 1.
Within the dimmer circuit 6, when the dimmer control voltage Vbri falls within an amplitude of the output Vtri of the triangular wave oscillation circuit 19 as shown in FIG. 15(A), the output Voff of the comparator is repeatedly turned between low level and high level as shown in FIGS. 15(B) and 15(C). During the period, in which the output Voff of the comparator 20 is held low level, the transistor Q3 becomes ON state. Therefore, as shown in FIG. 15(D), the sine wave is equivalently input to the piezoelectric transformer 1. However, as shown in FIG. 15(E), the output of the piezoelectric transformer 1 does not reach the predetermined output value until a period T1 being elapsed from initiation of input. Thus, the delay is caused in a period until reaching the predetermined output value is caused by mechanical vibration transmission speed within the piezoelectric transformer 1 and a feedback period of the drive frequency control.
Accordingly, when a continuing period of one ON period is set to be less than T1, the output of the piezoelectric transformer enters into the next OFF period before steady state is established to make illumination of the cold cathode tube unstable. Therefore, brightness of the cold cathode tube becomes unstable. By this, in a system varying brightness by varying the drive duty ratio, as shown in FIG. 16(A), the frequency of the triangular wave oscillation circuit 19 is set at a frequency F1, at which blinking may not be visually perceptible and below which blinking may be visually perceptible. The case where the drive ON period in one cycle is set at T1, the brightness becomes minimum. On the other hand, In this case, the output of the comparator 20 becomes as shown in FIG. 16(B), the drive frequency of the piezoelectric transformer 1 is FIG. 16(C), and the alternating current Io is shown in FIG. 16(D), respectively.
The minimum brightness concerns upon driving by the direct current input voltage VDD at the rated input voltage. Upon driving at the frequency F1 and at ON period T1, if the input voltage to the piezoelectric transformer inverter becomes less than the rated value, significant drawback should be encountered. Even by driving with the output of the triangular wave oscillation circuit 19 and the output of the comparator 20 as shown in FIGS. 17(A) and 17(B) under the same condition as shown in FIGS. 16(A) and 16(B), when the input voltage is less than the rated value, or when the input voltage to the piezoelectric transformer 1 is less than the rated value, since the input voltage to the piezoelectric transformer 1 does not satisfy the value for outputting the predetermined voltage and the current, frequency sweeping is repeated in the direction illustrated in FIG. 13.
However, in the case, since the frequency sweeping is interrupted during a drive OFF period for dimming, operation shown in FIG. 17(C) is performed. Since voltage input to the piezoelectric transformer 1 lacks, the alternating current Io flows slightly only when the drive frequency varies across the range close to the resonance frequency to cause phenomenon slightly illuminating the load 2 as shown in FIG. 17(D). At this time, blinking frequency is lower than F1, blinking becomes visually perceptible. The reason is that the sweeping period of the frequency control circuit 3 is expanded due to extinction period of the dimmer circuit 6 to increase a period to vary the drive frequency in f1.about.f2.about.f1 as shown in FIG. 13, and whereby to expand the period to causes light illumination to make the frequency less than the frequency F1, at which blinking is visually perceptible.
As a measure for this, there is a method to shorten a sweeping period of the drive frequency by making a time constant of the integration circuit 13 small. However, the piezoelectric transformer 1 has a property having high Q value to cause delay in response. Accordingly, there is a limit to shorten the sweeping period. Thus, the drive ON period T1 of the piezoelectric transformer 1 cannot be made sufficiently small to cause restrict dimming range.
The second problem resides in heating of parts of the drive circuit upon continuing sweeping of the frequency.
To the coils L1 and L2 shaping the input waveform to the piezoelectric transformer 1, a current shown in FIGS. 14(G) and 14(H) flows. The coil L1 is set so that the current value becomes zero immediately before the timing where the gate voltage Vg1 of the transistor Q1 becomes high level, and the coil L2 is set so that the current value becomes zero immediately before the timing where the gate voltage Vg2 of the transistor Q2 becomes high level. The setting is performed at a frequency where the alternating current Io becomes the desired value, namely, at the frequency shown by f0 in FIG. 13.
However, when the alternating current Io does not become the desired value, for example, when the load becomes open, the frequency sweeping shown in FIG. 13 is repeated. In the frequency higher than f0 within the frequency sweeping range, Vg1 and Vg2 become high level before the current flowing through the coils L1 and L2 become zero. At this moment, excessive current flows through the coils L1 and L2 and the transistors Q1 and Q2. When frequency sweeping is continued, the coils L1 and L2 and the transistors Q1 and Q2 are heated. In worst case, the coils L1 and L2 and the transistors Q1 and Q2 are heated in excess of guaranteed operation temperature, breakage of element or so forth can be caused.